1. Field of the Invention
The present invention relates generally to a method for manufacturing a semiconductor structure, more particularly, to a method for manufacturing a dual damascene structure adopting double patterning technique (DPT).
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are generally connected by several metal interconnecting layers commonly referred to as multi-level interconnects, and damascene process has been deemed a convenient and predominant method for forming the multi-level interconnects. Principally, the damascene process includes etching a dielectric material layer to form trench and/or via patterns, filling the patterns with conductive materials such as copper, and performing a planarization process.
Photolithography is an essential process in the fabrication of semiconductor ICs. Principally, the photolithography is to form designed patterns such as implantation patterns or layout patterns on at least a photomask, and then to precisely transfer such patterns to a photoresist layer by exposure and development processes. Subsequently, by performing processes such as ion implantation, etching process, or deposition, the complicated and sophisticated IC structure is obtained.
Along with miniaturization of semiconductor devices and progress in fabrication of semiconductor device, conventional lithography process meets the bottleneck due to printability and manufacturability. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, double patterning technique (DPT) is developed and taken as one of the most promising lithography technologies for 22 nm or 14 nm node patterning since it can increase the half-pitch resolution by up to two times using current infrastructures. However, the prior art DPT is confronted with a problem of via open induced by hard mask over confined as overlay misalignment.